`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:58:09 03/13/2014 
// Design Name: 
// Module Name:    pseudo_thermal_split 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module pseudo_thermal_split(
    input clk,
    input [7:0] pixel_data,
    output reg [7:0] red_out,
	 output reg [7:0] green_out,
	 output reg [7:0] blue_out
    );

parameter LOWER_BOUND = 1'd0;
parameter UPPER_BOUND = 8'd255;
parameter RED = 1'b0;
parameter GREEN = 1'b0;
parameter BLUE = 1'b0;

always @(posedge clk) begin
	if(pixel_data > LOWER_BOUND && pixel_data <= UPPER_BOUND) begin
		red_out <= RED;
		green_out <= GREEN;
		blue_out <= BLUE;
	end
	else begin
		red_out <= 1'b0;
		green_out <= 1'b0;
		blue_out <= 1'b0;
	end
end

endmodule
